The present invention relates generally to semiconductor device analysis and, more particularly, to devices and arrangements for enhancing the operability of semiconductor analysis.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the semiconductor packages which receive a die and on the exterior of the die, for connecting the packaged device to external systems, such as a printed circuit board.
As the manufacturing processes for semiconductor devices and integrated circuits increase in complexity, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early on is helpful for reducing the number of defective devices manufactured.
One type of semiconductor analysis involves conveniently directing perturbation signals, such as laser light, to a semiconductor device under test (DUT). When performing such analysis, however, many issues have to be managed. These issues include concerns such as laser leakage, calibration problems, and functional deficiencies. Further, a need exists for convenient approaches to presenting various types of perturbation signals to the DUT and managing the DUT""s response intelligently and efficiently.
The present invention is directed to an approach for improving semiconductor analysis. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
The present invention is directed to addressing needs discussed above and is further useful in connection with the example embodiments disclosed in the above-referenced patent documents. According to an example embodiment of the present invention, a system is adapted for analyzing a semiconductor die using two or more perturbation devices adapted to perturb the die. The system includes a test chamber and a docking arrangement adapted to dock with the test chamber and to hold the semiconductor die for analysis in the test chamber. A controller is adapted to control the perturbation, and a response from the die to the perturbation is acquired using a data acquisition arrangement. The data is used, for example, to analyze the die and/or to control the analysis system, and can be accomplished in a test chamber using a variety of perturbation devices.